Interrupts are a way of indicating to a processor that some event has occurred that needs processor attention, such as the completion of a read or write by a device. Historically, hardware interrupts used one of a small number of dedicated interrupt lines (typically designated INT0, INT1, . . . , INTx) that triggered the processor to run an interrupt handler to process the interrupt. The interrupt signaled on an INTx line is typically associated with a direct memory access (DMA) write by the source of the interrupt to provide needed information for use by the interrupt handler.
A more recent approach to interrupts, known as message-signaled interrupts (originally, MSI, but now MSI-X after the addition of certain extensions to the original MSI definition) that avoid the need for dedicated interrupt lines. An MSI-X interrupt is a message, for example sent over a PCI bus from the device to the processor, typically as a memory write or dedicated message type that results in a DMA write to a predetermined MSI-X address. The message written to the MSI-X address identifies the interrupt type, but data associated with the interrupt is written by a separate memory write, instead of in the message itself.
In high-speed communications networks, where each read or write completion on a communications link would ordinarily trigger an interrupt from a network interface controller (NIC) to a host processor, the host processor can become swamped with interrupts, without some technique for limiting when and how often interrupts may be signaled to the host processor. For example, two 10 Gigabit Ethernet ports if fully utilized may push up to ten million events per second to the host processor.
In conventional systems, a DMA occurs upon every send completion, typically DMAing a consumer pointer or other completion information to a host. This may lead to excessive DMAs, putting an excessive load on the host. In other conventional systems, a DMA for a send completion occurs only on interrupts, leading to excessive latency, which can be especially harmful at 10 Gb/s or higher link speeds. In yet other conventional systems, an interrupt occurs upon every receive completion, leading to excessive interrupts.